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Re: PICkit4 not ready for debugging
#4
版主
版主


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這下更慘了! 找不到元件的話連燒錄都會有問題。

建議檢查 ICSP 的接線? 減持一下 MCLR 腳除了有階提升電阻 10K 外是否也接電容到地? 如有接電容請移除後再試看看。

發表於: 2021/1/14 14:44
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Re: PICkit4 not ready for debugging
#3
初級會員
初級會員


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WDT off, OSC 設成IRCIO67, or IRCIO7
都顯示同樣的訊息


試過另一片板子顯示

Target Device ID (0x0) is an Invalid Device ID. Please check your connections to the Targe

MCU PIC18F2685是否這棵較不容易連PICKIT4?
有照data sheet建議調整MCLR pull up,試過33K, 10K

是否有其他建議?

發表於: 2021/1/13 16:27
best regards,
Anthony
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Re: PICkit4 not ready for debugging
#2
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"The target device is not ready for debugging" 通常是震盪器沒有震盪,PIC 沒有 Fosc 的驅動所以程式就無法執行。

建議在解決 HSPLL 外部震盪器之前先將震盪器的設定設成內部 RC 8MHz 先看看程式是否可以執行?

另一個設定就是在 Debug Mode 下,Watch-Dog Timer 一定要暫時先關閉,以避免系統又重置導致錯誤。

發表於: 2021/1/12 11:25
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PICkit4 not ready for debugging
#1
初級會員
初級會員


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device:PIC18F2685

config bits:
Address Name Value Field Option Category Setting
300001 CONFIG1H 86 OSC HSPLL Oscillator Selection bits HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
FCMEN OFF Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled
IESO ON Internal/External Oscillator Switchover bit Oscillator Switchover mode enabled
300002 CONFIG2L 1E PWRT ON Power-up Timer Enable bit PWRT enabled
BOREN BOHW Brown-out Reset Enable bits Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV 3 Brown-out Reset Voltage bits VBOR set to 2.1V
300003 CONFIG2H 06 WDT OFF Watchdog Timer Enable bit WDT disabled (control is placed on the SWDTEN bit)
WDTPS 8 Watchdog Timer Postscale Select bits 1:8
300005 CONFIG3H 84 PBADEN OFF PORTB A/D Enable bit PORTB<4:0> pins are configured as digital I/O on Reset
LPT1OSC ON Low-Power Timer 1 Oscillator Enable bit Timer1 configured for low-power operation
MCLRE ON MCLR Pin Enable bit MCLR pin enabled; RE3 input pin disabled
300006 CONFIG4L C1 STVREN ON Stack Full/Underflow Reset Enable bit Stack full/underflow will cause Reset
LVP OFF Single-Supply ICSP Enable bit Single-Supply ICSP disabled
BBSIZ 1024 Boot Block Size Select bits 1K words (2K bytes) Boot Block
XINST ON Extended Instruction Set Enable bit Instruction set extension and Indexed Addressing mode enabled
300008 CONFIG5L 3F CP0 OFF Code Protection bit Block 0 (000800-003FFFh) not code-protected
CP1 OFF Code Protection bit Block 1 (004000-007FFFh) not code-protected
CP2 OFF Code Protection bit Block 2 (008000-00BFFFh) not code-protected
CP3 OFF Code Protection bit Block 3 (00C000-00FFFFh) not code-protected
CP4 OFF Code Protection bit Block 4 (010000-013FFFh) not code-protected
CP5 OFF Code Protection bit Block 5 (014000-017FFFh) not code-protected
300009 CONFIG5H C0 CPB OFF Boot Block Code Protection bit Boot block (000000-0007FFh) not code-protected
CPD OFF Data EEPROM Code Protection bit Data EEPROM not code-protected
30000A CONFIG6L 3F WRT0 OFF Write Protection bit Block 0 (000800-003FFFh) not write-protected
WRT1 OFF Write Protection bit Block 1 (004000-007FFFh) not write-protected
WRT2 OFF Write Protection bit Block 2 (008000-00BFFFh) not write-protected
WRT3 OFF Write Protection bit Block 3 (00C000-00FFFFh) not write-protected
WRT4 OFF Write Protection bit Block 4 (010000-013FFFh) not write-protected
WRT5 OFF Write Protection bit Block 5 (014000-017FFFh) not write-protected
30000B CONFIG6H E0 WRTC OFF Configuration Register Write Protection bit Configuration registers (300000-3000FFh) not write-protected
WRTB OFF Boot Block Write Protection bit Boot block (000000-0007FFh) not write-protected
WRTD OFF Data EEPROM Write Protection bit Data EEPROM not write-protected
30000C CONFIG7L 3F EBTR0 OFF Table Read Protection bit Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
EBTR1 OFF Table Read Protection bit Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 OFF Table Read Protection bit Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 OFF Table Read Protection bit Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTR4 OFF Table Read Protection bit Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
EBTR5 OFF Table Read Protection bit Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
30000D CONFIG7H 40 EBTRB OFF Boot Block Table Read Protection bit Boot block (000000-0007FFh) not protected from table reads executed in other blocks





*****************************************************



Calculating memory ranges for operation...

Erasing...

The following memory area(s) will be programmed:
program memory: start address = 0x0, end address = 0x35bf
program memory: start address = 0x41c0, end address = 0x49ff
program memory: start address = 0x5000, end address = 0xac3f
program memory: start address = 0xafc0, end address = 0xafff
configuration memory

Script GetVersionDE failed with status Type = runScript, Script name = GetVersionDE, Status = 0xa00
.
The target device is not ready for debugging. Please check your configuration bit settings and program the device before proceeding. The most common causes for this failure are oscillator and/or PGC/PGD settings.

發表於: 2021/1/11 17:07
best regards,
Anthony
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