#define FCY 7372800*2 //one instruction frequency //constract initial _FOSC(CSW_FSCM_OFF & XT_PLL8); _FWDT(WDT_OFF); _FBORPOR(0x008300); //enable MCLR, PWMPIN=1(controlled by port at device reset),HPOL=1 and LPOL=1 active high output polarity _FGS(CODE_PROT_OFF);
PTCONbits.PTSIDL=1; //PWM halt when idle mode PTCONbits.PTOPS=0x0; //interrupt 1:1 postscale PTCONbits.PTCKPS=0x0; //1:1 prescale PTCONbits.PTMOD=0x0; //operating in a free running mode
PTPERbits.PTPER=0x024D; //PWM time base period register PDC1=0x024D; //PWM1 50% PDC2=0x024D; //PWM2 50%
PWMCON1bits.PMOD1=1; //independent PWM 1H 1L output mode PWMCON1bits.PMOD2=1; //independent PWM 2H 2L output mode PWMCON1bits.PEN1H=1; //PWM1H enabled for PWM output PWMCON1bits.PEN1L=1; //PWM1L enabled for PWM output PWMCON1bits.PEN2H=1; //PWM2H enabled for PWM output PWMCON1bits.PEN2L=1; //PWM2L enabled for PWM output
PWMCON2bits.SEVOPS=0x0; //special event trigger 1:1 postscale PWMCON2bits.OSYNC=1; //overrides synchronous PWM time base PWMCON2bits.UDIS=0; //enable updata duty cycle PTCONbits.PTEN=1; //base timer open }