Slave 收到一筆完整的 8-bit 資料並回 ACK 後會將 SCL 拉成 Low Level 以暫緩 Master 送出下一筆資料。可以在接收完成後利用清除 CKP 位元將 SCL Release to Hi

請問大家,
我寫了一段i2c slave的程式，在slave接收master是正常，但是當master要對slave進行讀取時就會不正常了。當slave在接收到master傳來的address且rw=1時，slave會有回應ack但接下來scl(clock)、sda就一直為low了以致於slave不能傳master想要的data給master了。
請問大家是哪裡出錯呢?
謝謝


void initial_i2c()
{
TRISC3=1;
TRISC4=1; //i2c slave mode the RC3,RC4 are input
SSPADD=(address<<1); //set the I2C slave address
SSPIE=1; //enble SSP interrupt
SSPIF=0; //clear SSP interrupt flag

//SSPSTAT resgister setup//----------------------------------------------------------------------
SMP=1; //i2c standard speed mode(100KHz~1MHz)
//----------------------------------------------------------------------------------------------//
//SSPCON resgister setup//------------------------------------------------------------------------
SSPEN=1; //set the RC3 as SCL, RC4 as SDA
SSPM0=0;
SSPM1=1;
SSPM2=1;
CKP=1; //added on 5.19
SSPM3=0; //I2C slave mode, 7 bit address
WCOL=0; //clear collision detect flag
SSPOV=0; //clear receive overflow indicate bit
SSPSTAT=0;
//----------------------------------------------------------------------------------------------//
}

void interrupt isr_i2c(void) //ISR program
{
if(SSPIF==1)
{
i2c_handle();
if(SSPOV)
{
SSPOV=0;
}
SSPIF=0;
}
}
byte read_i2c(void)
{
temp=SSPBUF;
return temp ;
}

void write_i2c(byte write_data)
{
while(BF==1);
WCOL=0;
do
{
SSPBUF=write_data;
}while(WCOL);
CKP=1;
}

void i2c_handle(void)
{
if((DA==0)&&(RW==0)&&(BF==1)&&(START==1))
{
data=read_i2c();
receive1=data;
}
if((DA==1)&&(RW==0)&&(BF==1)&&(START==1))
{
data=read_i2c();
receive2=data;
}

if((DA==0)&&(RW==1)&&(BF==0)&&(START==1))
{
if(receive2==0x01)
{
write_i2c(0xbb);
}
if(receive2==0x02)
{
write_i2c(0xcc);
}
}
if((DA==1)&&(RW==1)&&(BF==0)&&(START==1))
{
if(receive2==0x01)
{
write_i2c(0xbb);
}
if(receive2==0x02)
{
write_i2c(0xcc);
}
}
if((DA==1)&&(RW==0)&&(BF==0)&&(START==1))
{
data=read_i2c();
}
}