有關內建 FRC 要到 480MHz 的設定在書上頁有提到: This method derives the 480 MHz clock: • FRC Clock with high-range Option and TUN<3:0> = 0111 is = 15 MHz • PLL enabled • PWM clock = 15 x 32 = 480 MHz • FCY = 480 MHz/16 = 30 MHz = 30 MIPS
If the PLL is disabled, • FRC Clock (with high-range Option and TUN<3:0> = 0111) is = 15MHz • FCY = 15 MHz/2 = 7.5 MHz = 7.5 MIPS
內建的 FRC 可以到達 451MHz 的頻率,可以參考一下FOSC< FRANGE> 的位元資訊 (Page 196) : Frequency Range Select for FRC and PLL bit Acts like a “Gear Shift” feature that enables the dsPIC DSC device to operate at reduced MIPS at a reduced supply voltage (3.3V) 1 = “High Range” (FRC operates at a nominal 14.55 MHz, PLL VCO at a nominal 451 MHz. (480 max)) 0 = “Low Range” (FRC operates at a nominal 9.7 MHz, PLL VCO at a nominal 301 MHz (320 max))