If using C, just divide the signed value by 2.

If using assembly, dsPIC has some DIV and SHIFT instructions which can keep the sign of the variable.

Thanks for your answer. BBL

For question3, a 12bit ADC output format can be one of the following:
1. signed fractional sddd dddd dddd 0000
2. unsgined fractional dddd dddd dddd 0000
3. signed integer
4. unsigned integer

If I have my analogue input range from 0.0V to 3.3V and signed fractional is chosen, the ADC output value will be -1 (0.0V) to +1 (3.3V). How can we change the range to what you mentioned in Answer3?

1. Until all of the 64 point data is ready, the output of the 64-pint FFT has no meaning.
2. I think, if you use FFT continuously, except the 1st FFT, all following FFT doesn't require zero padding.
3. You should make 1.65V to represent 0, 3.3V to represent +0.5, and 0V to represent -0.5V. dsPIC signed fractional format can help.

Hi,

I am a newbie in DSP processing. Just want to ask some questions which might be very easy.

In the code example CE108, it mentioned:
"inputsignal_square1khz.c" in the array named sigCmpx[]". This array should be of length, FFT_BLOCK_LENGTH and
type "fractcomplex". So, for a 64-pt FFT, it should contain only 64 data samples and padded initially with 64 zeroes. This array
stores the output of the complex FFT operation and eventually stores the magnitudes of the frequency bins."

1. Why do we need 64 zero paddings? I am not quite understand.

2. Also, if I change the source of input signal from "inputsignal_square1khz.c" to an ADC input, how many samples will I
need in order to perform FFT? Will I need to include the zero padding as well?

3. As the document also mentioned that the amplitude of input signal must be in the range +0.5 to -0.5, if I got a signal from
0 to 3.3V, will I need to scale it down to 0 to 0.5V before I perform the FFT?

Many thanks